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MIPI D-PHY Pattern Generator数据包发生器

The stand-alone DPhy Generator (P344) can generate CSI and DSI protocol and pattern stimulus on a MIPI DPhy bus for receiver testing, notably supporting the DPhy 1.2 specification.

The DPhy Generator is connected via USB to a host computer that runs the DPhyGenCtl
software. It has the following capabilities:

  • Connects via either USB2 or USB3, allowing for fast program download times
  • Contains internal pattern generator with 2 GB of program memory
  • Supports one to four DPhy lanes, supporting frequencies up to 4.5 Gb/s
  • Lane outputs are via SMA connectors
  • Provides up to ~4.5 ns of independent lane skew below 3.2 Gb/s
  • Provides ~320ps of skew above 3.2 Gb/s.
  • Provides real-time, per-lane, high and low HS voltage adjustments and common high and low LP voltage adjustments.
  • Supports configuration and adjustment of DPhy bus timing.
  • Provides 4 KB receive buffer for DUT response capture of LP data.
  • Supports lane 0 LP contention detection.
  • Implements arbitrary logical-to-physical lane output mapping.
  • Provides a configurable Trig Out signal, which can be asserted via MIPI stream and/or software control.

Compared to our previous Logical Analyzer( LA) based PG3A+P338 solution, this latest stand-alone solution has many big enhancements:


The latest Software DphyGenCtl, compared its previous PGRemote For P338, also have many advantages:

  • Comprehensive video support:
    - Support for 3D stereoscopic frame construction (DSI 1.2).
    - Purchase option for encoding and sending of DSC video frames (DSI 1.2).
    - Common source input image file formats (jpg, png, tiff, gif), used for both videomode and Write Memory commands.
    - Automatic resizing of input images (in software) to fit display or camera dimensions.
  • Basic test pattern generation via naming syntax (syntax dialog provided).
    - Convenient image preview function in GUI.
    - Automated CSI/DSI video-mode frame generation based on user frame timing.
    - Automatic partitioning of single Write Memory command into multiple Write
  • Memory command sequence.
    - Video-mode frames can be added to macros.
    - Video-mode frames can be constructed with a single-bit error at a given line and bit position.
  • Generic File command support:
    - Uses text file description to describe mixed low-level LP/HS transitions and packet definition.
    - Allows nearly-arbitrary data lane signal generation for conformance testing.
    - Provides higher-level embedded commands for easy command definition, including HS burst entry, HS burst exit, clock on, clock off sequences. Also, automatic ECC and CRC generation.
    - Supports nested files for reuse of common definitions.
  • Support for low-level Phy testing:
    - Low-level test HS burst sequences using user-defined or PRBS data.
    - User configuration of bus timings, e.g. HSPrepare, HSZero, HSTrail, HSExit, etc.
    - New flexible bus timing specification in component units of ns, UI, and TLPX, allowing for frequency agile configurations.
  • Powerful and easy-to-use GUI controls for command manipulation:
    - Simple definition, naming, and sending of commands, including video-mode
    commands.

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